As semiconductor technology has advanced into the deep submicron regime, the power supply voltage is scaled down in concert with the scaling down of transistor dimensions. Nevertheless, input/output (I/O) standards from higher-voltage regimes may still need to be supported. But the thick-oxide transistors in modern high-density integrated circuits may not be able to accommodate any voltage higher than some maximum level such as two volts across their gate-source, gate-drain, or source-drain junctions. To safely receive input signals with voltages that exceed such maximum levels, it is conventional to use native transistors in the integrated circuit's input receiver.
An example conventional input receiver 100 is shown in FIG. 1A. A native NMOS pass transistor 105 has its gate driven by the internal power supply voltage VDD. This internal voltage VDD is lower than a power supply voltage VDDX that is cycled to by a VDDX-domain input signal 102 received at a drain of native pass transistor 105. The level for VDDX depends upon the signaling protocol for input signal 102. For example, one signaling protocol may have input signal 102 cycle between 0 and 3.3V (VDDX) according to its frequency. In contrast, VDD may equal 1.8V or 1.65 V, which is a safer level for modern devices. In that regard, if 3.3V were impressed across any pair of terminals for native pass transistor 105 (drain-to-source, gate-to-source, or gate-to-drain), native pass transistor 105 may fail. More generally, VDD equals approximately one-half of VDDX, regardless of the level for VDDX as determined by the signaling protocol.
As input signal 102 rises to VDD, it passes through to the drain of native pass transistor 105 since its voltage threshold is zero volts. The gate-to-source voltage for native pass transistor 105 eventually drops to zero, which prevents the source of native pass transistor from rising higher than VDD. Although the drain continues to rise to 3.3V in a cycle of input signal voltage 102, native pass transistor 105 is not strained since there is no more than a VDD voltage difference between its drain and source. Similarly, there is never more than a VDD voltage difference between the gate and drain or between the gate and source of native pass transistor 105.
A receiver such as an inverter 110 powered by the VDD power supply voltage inverts the source voltage to produce a VDD-domain or stepped-down output signal 115 from VDDX-domain input signal 102. Inverter 110 drives output signal 115 to internal circuitry (not illustrated) of the integrated circuit that includes input receiver 100. Although native pass transistor 105 avoids voltage strain problems in converting VDDX-domain input signal 102 into a VDD-domain output signal 115, input receiver 100 suffers from a number of problems. For example, an external source drives input signal 102. Input receiver 100 has no control over this external source. Native pass transistor 105 thus passes whatever duty cycle and slew rate it receives through to inverter 110. The duty cycle and slew rate for VDD-domain output signal 115 from inverter 110 may thus be unacceptably distorted. In addition, further distortion results from input signal 102 oscillating between voltage minimums and voltage maximums that differ from the desired levels of ground and VDDX. Moreover, native devices such as native pass transistor 105 are very sensitive to process variations. Use of input receiver 100 is thus limited to relatively low input signal frequencies such as in the tens of MHz to satisfy a +/−5% duty cycle error requirement.
Accordingly, there is a need in the art for step-down input receivers providing more accurate performance in higher frequency domains.